pos logs class span input pan reg 两个 left
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--调节两个LED灯亮度
- module led_pwm (
- clk,
- rst,
- //cnt1_pwm,
- out1,
- out2,
- out3,
- out4
- );
- input clk, rst;
- //input [19:0] count_pwm;
- output reg out1, out2;
- output out3, out4;
- reg [19:0] cnt;
- reg [19:0] cnt1_pwm = 21‘d2, cnt2_pwm = 21‘d52_4288;
- reg [25:0] cnt_s;
- always @ (posedge clk, negedge rst)
- if (!rst)
- begin
- cnt_s <= 0;
- cnt1_pwm <= 21‘d1;
- cnt2_pwm <= 21‘d52_4288;
- end
- else if (cnt_s == 26‘d1000_0000) //计0.2秒
- begin
- cnt_s <= 0;
- cnt1_pwm <= {cnt1_pwm[18:0], cnt1_pwm[19]}; //调节脉宽
- cnt2_pwm <= {cnt2_pwm[0], cnt2_pwm[19:1]};
- //cnt1_pwm <= (cnt1_pwm >> 2)|(cnt1_pwm << 19);//right
- //cnt2_pwm <= (cnt2_pwm << 2)|(cnt2_pwm >> 19);//left
- end
- else
- cnt_s <= cnt_s + 1;
- //
- always @ (posedge clk, negedge rst)
- if (!rst)
- cnt <= 21‘h0;
- else if (cnt == 21‘d55_0000) //一个周期
- cnt <= 21‘b0;
- else
- cnt <= cnt + 1‘b1;
- // pwm生成
- always @ (posedge clk, negedge rst)
- if (!rst)
- out1 <= 1‘b0;
- else if (cnt <= cnt1_pwm)
- out1 <= 1‘b0;
- else
- out1 <= 1‘b1;
- always @ (posedge clk, negedge rst)
- if (!rst)
- out2 <= 1‘b0;
- else if (cnt <= cnt2_pwm)
- out2 <= 1‘b0;
- else
- out2 <= 1‘b1;
- assign out3 = 1‘b0;
- assign out4 = 1‘b0;
- endmodule
PWM----调节LED亮度
来源: http://www.bubuko.com/infodetail-2331766.html